This invention relates generally to analog to digital converters (ADC), and more particularly the invention relates to a pipelined ADC.
A number of different converters have been developed for the conversion of analog signals to digital signals. These include many types, such as the integrating ADC which is highly accurate but slow (1-10 kHz), the successive approximation which is medium speed (less than 500 kHz) with medium resolution, the flash ADC which is very high speed (greater than 1 mHz) but with low to medium resolution, and the pipeline ADC which is highly accurate with medium to high speed (greater than 1 mHz).
The integrating ADC uses a digital to analog converter (DAC) to obtain the ADC function. In the most basic form, this scheme uses a digital counter, a DAC, and a comparator to obtain the ADC function. The counter is set to start counting up from zero by an external signal, and the digital outputs are fed to the DAC which produces an analog output voltage in accordance with a counter digital count. At each count step, the DAC output voltage is compared with the input analog signal and, when the DAC output voltage is equal to or higher than the analog input, the counter is stopped. The count and the stop counter represents the magnitude of the analog input signal.
The successive approximation ADC makes an intelligent decision to quickly locate the signal prior to modifying a counter. It obtains its enhancements in first determining which half (above or below half scale) a signal is in prior to changing the counter. For example, starting with the most significant bit set results in the following logic. If the comparator trips, the signal is in the lower half. If the comparator does not trip, the signal is in the upper half. This usually reduces the time to locate the actual level of this signal.
The flash ADC is a technique which is widely used at present. Measurement is straight forward and nearly instantaneous without the time consuming counter as used in the earlier ADCs. A series resistor divider network provides references to a number of analog comparators. There are as many taps in the divider network and comparators as bits of resolution. Each tap provides a stable step reference voltage to its associated comparator.
Traditional flash architectures have been upgraded using interpolating techniques. As disclosed in U.S. Pat. No. 5,298,814, analog to digital converters combine the concepts of residue amplification and averaging to simplify the circuit implementation of high order, high speed analog to digital converters. The circuitry uses active transconductor devices, for example a pair of CMOS inverters having a common drain as an output, a first input connected to the gates of one inverter, a second input connected to the gates of the other inverter, and with the inverters operating in a linear gain range. Such active analog averaging circuits can be employed in an analog to digital converter employing residue amplification to provide an improved high order, high speed device.
A standard pipeline approach uses a sample and hold, one bit DAC, a subtractor, and a multiplier (.times.2). An analog sample is first frozen in time by the sample and hold circuit to allow the processing of that sample by subsequent circuits. At the output of the sample and hold, a summing circuit subtracts a voltage reference from the sample. The reference voltage is designed to be one-half of the analog full scale input range which allows the circuit to function simply on whether the sample is above or below the reference, that is, in the upper or lower half of the input range.
The present invention is directed to a pipelined ADC having an increased operating speed which utilizes the basic active interpolating technique applied in a pipeline architecture.